context-ext-smartnics.proto

// Copyright 2022-2023 ETSI TeraFlowSDN - TFS OSG (https://tfs.etsi.org/)
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//      http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

// References:
// https://www.nvidia.com/content/dam/en-zz/Solutions/networking/ethernet-adapters/connectX-6-dx-datasheet.pdf
// converged accel: https://www.nvidia.com/content/dam/en-zz/Solutions/gtcf21/converged-accelerator/pdf/datasheet.pdf
// bluefield-2 = connectX-6 + DPUs
// conv_accel = bluefield-2 + GPU

syntax = "proto3";
package context-ext-smartnics;

import "context";
import "kpi_sample_types.proto";

message SmartnicsCapabilities {
    string vendor = 1;
    string model = 2;
    string serial_number = 3;
    repeated Transceiver transceivers = 4;
    repeated DPU dpus = 5;
    repeated GPU gpus = 6;
}

enum TransceiverPortTypeEnum {
    TRANSCEIVER_PORT_TYPE_UNDEFINED = 0;
    TRANSCEIVER_PORT_TYPE_SFP       = 1;
    TRANSCEIVER_PORT_TYPE_SFP_PLUS  = 2;
    TRANSCEIVER_PORT_TYPE_QSFP_28   = 3;
    TRANSCEIVER_PORT_TYPE_QSFP_56   = 4;
    TRANSCEIVER_PORT_TYPE_QSFP_DD   = 5;
}

enum TransceiverPortSpeedEnum {
    TRANSCEIVER_PORT_SPEED_UNDEFINED = 0;
    TRANSCEIVER_PORT_SPEED_1G        = 1;
    TRANSCEIVER_PORT_SPEED_10G       = 2;
    TRANSCEIVER_PORT_SPEED_25G       = 3;
    TRANSCEIVER_PORT_SPEED_40G       = 4;
    TRANSCEIVER_PORT_SPEED_100G      = 5;
    TRANSCEIVER_PORT_SPEED_200G      = 6;
    TRANSCEIVER_PORT_SPEED_400G      = 7;
    TRANSCEIVER_PORT_SPEED_800G      = 8;
}

message Transceiver {
    TransceiverPortTypeEnum port_type = 1;
    repeated TransceiverPortSpeedEnum port_speeds = 2;
    repeated kpi_sample_types.KpiSampleType kpi_sample_types = 3;
}

message DPU {
    uint32 num_cores = 1;
    repeated DPU_Core cores = 2;
    repeated DPU_Memory memories = 3;
}

enum DpuCoreArchitectureEnum {
    DPU_CORE_ARCHITECTURE_UNDEFINED = 0;
    DPU_CORE_ARCHITECTURE_32BIT     = 1;
    DPU_CORE_ARCHITECTURE_64BIT     = 2;
}

message DPU_Core {
    string model = 1; // Armv8 A72
    DpuCoreArchitectureEnum architecture = 2; 
    uint64 l2_cache_size_mb = 3;
    uint64 l3_cache_size_mb = 4;
}

message DPU_Memory {
    string RamMemoryType = 1; //On-Board DDR4
    string eMMCMemoryType = 2; //eMMC
    DpuRamMemorySizeGB RamMemorySizeGB = 3; 
    DpueMMCMemorySizeGB eMMCMemorySizeGB = 4; 
}

enum DpuRamMemorySizeGB {
    DPU_MEMORY_DDR4_RAM_UNDEFINED = 0;
    DPU_MEMORY_DDR4_RAM_16GB = 1;
    DPU_MEMORY_DDR4_RAM_32GB = 2;
}

enum DpueMMCMemorySizeGB {
    DPU_MEMORY_eMMC_UNDEFINED = 0;
    DPU_MEMORY_eMMC_32GB = 1;
    DPU_MEMORY_eMMC_64GB = 2;
    DPU_MEMORY_eMMC_128GB = 3;
}

enum Architecture {
    ARCH_UNDEFINED = 0;
    ARCH_AMPERE = 1;
}

enum ComputeCapabilities {
    MIG_UNDEFINED = 0;
    MIG_4_AT_6GB = 1;
    MIG_2_AT_12GB = 2;
    MIG_1_AT_24GB = 3;
}


message GPU {
    Architecture architecture = 1; //AMPERE?
    ComputeCapabilities compute_capabilities = 2; //MIG?
    uint64 memory_size_gb = 3; //24 GB HBM2
    uint32 num_CUDA_cores = 4; //3804
    uint32 num_Tensor_cores = 5; //224
    uint32 peak_fp_32 = 6; //10.3TF
    uint32 peak_fp_64 = 7; //5.2TF
    uint32 peak_fp_64_tensor_core = 8; //10.3TF
}