Update Context SmartNICs

proto/context-ext-smartnics.proto

@@ -13,8 +13,6 @@
 // limitations under the License.
 
 // References:
-// https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/products/a30-gpu/pdf/a30-datasheet.pdf
-// https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/documents/datasheet-nvidia-bluefield-2-dpu.pdf
 // https://www.nvidia.com/content/dam/en-zz/Solutions/networking/ethernet-adapters/connectX-6-dx-datasheet.pdf
 // converged accel: https://www.nvidia.com/content/dam/en-zz/Solutions/gtcf21/converged-accelerator/pdf/datasheet.pdf
 
@@ -77,24 +75,50 @@ enum DpuCoreArchitectureEnum {
 
 message DPU_Core {
     string model = 1; // Armv8 A72
-    enum   DpuCoreArchitectureEnum architecture = 2; // 64-bit
-    // define cache:
-    // -- 1MB L2 cache per 2 cores
-    // -- 6MB L3 cache with plurality of eviction policies
+    enum   DpuCoreArchitectureEnum architecture = 2; 
+    uint64 l2_cache_size_mb = 3;
+    uint64 l3_cache_size_mb = 4;
 }
 
 message DPU_Memory {
-    // define RAM and eMMC
-    // -- DDR4 DIMM Support
-    // -- > Single DDR4 DRAM controller
-    // -- > 16GB / 32GB of on-board DDR4
-    // -- > ECC error protection support
+    string RamMemoryType = 1; //On-Board DDR4
+    string eMMCMemoryType = 2; //eMMC
+    enum DpuRamMemorySizeGB RamMemorySizeGB = 3; 
+    enum DpueMMCMemorySizeGB eMMCMemorySizeGB = 4; 
+}
+
+enum DpuRamMemorySizeGB {
+    DPU_MEMORY_DDR4_RAM_UNDEFINED = 0;
+    DPU_MEMORY_DDR4_RAM_16GB = 1;
+    DPU_MEMORY_DDR4_RAM_32GB = 2;
+}
+
+enum DpueMMCMemorySizeGB {
+    DPU_MEMORY_eMMC_UNDEFINED = 0;
+    DPU_MEMORY_eMMC_32GB = 1;
+    DPU_MEMORY_eMMC_64GB = 2;
+    DPU_MEMORY_eMMC_128GB = 3;
 }
 
 message GPU {
-    enum Architecture architecture = 1;
-    enum ComputeCapabilities compute_capabilities = 2;
-    uint64 memory_size_mb = 3;
-    uint32 num_cores = 4;
-    // complete with specs of GPU
+    enum Architecture architecture = 1; //AMPERE?
+    enum ComputeCapabilities compute_capabilities = 2; //MIG?
+    uint64 memory_size_gb = 3; //24 GB HBM2
+    uint32 num_CUDA_cores = 4; //3804
+    uint32 num_Tensor_cores = 5; //224
+    uint32 peak_fp_32 = 6; //10.3TF
+    uint32 peak_fp_64 = 7; //5.2TF
+    uint32 peak fp_64_tensor_core = 8; //10.3TF
+}
+
+enum Architecture {
+    ARCH_UNDEFINED = 0;
+    ARCH_AMPERE = 1;
+}
+
+enum ComputeCapabilities {
+    MIG_UNDEFINED = 0;
+    MIG_4_AT_6GB = 1;
+    MIG_2_AT_12GB = 2;
+    MIG_1_AT_24GB = 3;
 }