Loading src/opticalcontroller/RSA.py +3 −2 Original line number Diff line number Diff line Loading @@ -871,17 +871,20 @@ class RSA(): self.db_flows[self.flow_id]["bitrate"] = rate self.db_flows[self.flow_id]["bidir"] = bidir #@Chafy links, path = self.compute_path(src, dst) if len(path) < 1: self.null_values(self.flow_id) return self.flow_id op, num_slots = map_rate_to_slot(rate) #@Chafy c_slots, l_slots, s_slots = self.get_slots(links, num_slots) if debug: print(c_slots) print(l_slots) print(s_slots) #@Chafy if len(c_slots) > 0 or len(l_slots) > 0 or len(s_slots) > 0: flow_list, band_range, slots, fiber_f, fiber_b = self.select_slots_and_ports(links, num_slots, c_slots, l_slots, s_slots, bidir) Loading Loading @@ -1189,8 +1192,6 @@ class RSA(): self.null_values(self.flow_id) return self.flow_id else: print("error") self.null_values(self.flow_id) Loading Loading
src/opticalcontroller/RSA.py +3 −2 Original line number Diff line number Diff line Loading @@ -871,17 +871,20 @@ class RSA(): self.db_flows[self.flow_id]["bitrate"] = rate self.db_flows[self.flow_id]["bidir"] = bidir #@Chafy links, path = self.compute_path(src, dst) if len(path) < 1: self.null_values(self.flow_id) return self.flow_id op, num_slots = map_rate_to_slot(rate) #@Chafy c_slots, l_slots, s_slots = self.get_slots(links, num_slots) if debug: print(c_slots) print(l_slots) print(s_slots) #@Chafy if len(c_slots) > 0 or len(l_slots) > 0 or len(s_slots) > 0: flow_list, band_range, slots, fiber_f, fiber_b = self.select_slots_and_ports(links, num_slots, c_slots, l_slots, s_slots, bidir) Loading Loading @@ -1189,8 +1192,6 @@ class RSA(): self.null_values(self.flow_id) return self.flow_id else: print("error") self.null_values(self.flow_id) Loading