Commit b4c87481 authored by Matthias Simon's avatar Matthias Simon
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Add first example

parent a748a6bf
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+69 −0
Original line number Original line Diff line number Diff line
// @verdict: pass accept, ttcn3verdict: pass
module InterleaveWithDefault {
	type port Port {
		integer
	}

	type component C {
		port Port p;
	}

	testcase toplevel() runs on C {
		var boolean ok := false;

		p.send(3);

		activate(consumeMessage());

		// the successful default will terminate bellow interleave
		// and continue execution after the block
		interleave {
			[] p.receive(1) {
				setverdict(fail);
			}

			[] p.receive(2) {
				setverdict(fail);
			}
		}
		setverdict(pass);
	}

	testcase nestedAlt() runs on C {
		var boolean ok := false;

		p.send(1);
		p.send(4);

		activate(consumeMessage());

		// Message `1` is consumed and interleave is waiting for
		// in first branch for a message 3 or a message 2.
		// Activated default will terminate the nested alt block
		// and will continue is execution of `ok := true`.
		interleave {
			[] p.receive(1) {
				p.receive(3);
				ok := true;
			}

			[] p.receive(2) {
				setverdict(fail);
			}
		}

		setverdict(pass);
		if (not ok) {
			setverdict(fail);
		}
	}

	altstep consumeMessage() runs on C {
		p.receive;
	}

	control {
		execute(toplevel(), 10);
		execute(nestedAlt(), 10);
	}
}