From ab9a0dcd86da5bcd9e2230b9b9bbd18b3c696797 Mon Sep 17 00:00:00 2001
From: Jose Luis Carcel <jose.carcel@atos.net>
Date: Wed, 26 Jul 2023 08:18:08 +0000
Subject: [PATCH] Create Context Smartnics
---
proto/context-ext-smartnics.proto | 100 ++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 proto/context-ext-smartnics.proto
diff --git a/proto/context-ext-smartnics.proto b/proto/context-ext-smartnics.proto
new file mode 100644
index 000000000..f4783da73
--- /dev/null
+++ b/proto/context-ext-smartnics.proto
@@ -0,0 +1,100 @@
+// Copyright 2022-2023 ETSI TeraFlowSDN - TFS OSG (https://tfs.etsi.org/)
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// References:
+// https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/products/a30-gpu/pdf/a30-datasheet.pdf
+// https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/documents/datasheet-nvidia-bluefield-2-dpu.pdf
+// https://www.nvidia.com/content/dam/en-zz/Solutions/networking/ethernet-adapters/connectX-6-dx-datasheet.pdf
+// converged accel: https://www.nvidia.com/content/dam/en-zz/Solutions/gtcf21/converged-accelerator/pdf/datasheet.pdf
+
+// bluefield-2 = connectX-6 + DPUs
+// conv_accel = bluefield-2 + GPU
+
+syntax = "proto3";
+package context-ext-smartnics;
+
+import context;
+import "kpi_sample_types.proto";
+
+message SmartnicsCapabilities {
+ string vendor = 1;
+ string model = 2;
+ string serial_number = 3;
+ repeated Transceiver transceivers = 4;
+ repeated DPU dpus = 5;
+ repeated GPU gpus = 6;
+}
+
+enum TransceiverPortTypeEnum {
+ TRANSCEIVER_PORT_TYPE_UNDEFINED = 0;
+ TRANSCEIVER_PORT_TYPE_SFP = 1;
+ TRANSCEIVER_PORT_TYPE_SFP_PLUS = 2;
+ TRANSCEIVER_PORT_TYPE_QSFP_28 = 3;
+ TRANSCEIVER_PORT_TYPE_QSFP_56 = 4;
+ TRANSCEIVER_PORT_TYPE_QSFP_DD = 5;
+}
+
+enum TransceiverPortSpeedEnum {
+ TRANSCEIVER_PORT_SPEED_UNDEFINED = 0;
+ TRANSCEIVER_PORT_SPEED_1G = 1;
+ TRANSCEIVER_PORT_SPEED_10G = 2;
+ TRANSCEIVER_PORT_SPEED_25G = 3;
+ TRANSCEIVER_PORT_SPEED_40G = 4;
+ TRANSCEIVER_PORT_SPEED_100G = 5;
+ TRANSCEIVER_PORT_SPEED_200G = 6;
+ TRANSCEIVER_PORT_SPEED_400G = 7;
+ TRANSCEIVER_PORT_SPEED_800G = 8;
+}
+
+message Transceiver {
+ TransceiverPortTypeEnum port_type = 1;
+ repeated TransceiverPortSpeedEnum port_speeds = 2;
+ repeated kpi_sample_types.KpiSampleType kpi_sample_types = 3;
+}
+
+message DPU {
+ uint32 num_cores = 1;
+ repeated DPU_Core cores = 2;
+ repeated DPU_Memory memories = 3;
+}
+
+enum DpuCoreArchitectureEnum {
+ DPU_CORE_ARCHITECTURE_UNDEFINED = 0;
+ DPU_CORE_ARCHITECTURE_32BIT = 1;
+ DPU_CORE_ARCHITECTURE_64BIT = 2;
+}
+
+message DPU_Core {
+ string model = 1; // Armv8 A72
+ enum DpuCoreArchitectureEnum architecture = 2; // 64-bit
+ // define cache:
+ // -- 1MB L2 cache per 2 cores
+ // -- 6MB L3 cache with plurality of eviction policies
+}
+
+message DPU_Memory {
+ // define RAM and eMMC
+ // -- DDR4 DIMM Support
+ // -- > Single DDR4 DRAM controller
+ // -- > 16GB / 32GB of on-board DDR4
+ // -- > ECC error protection support
+}
+
+message GPU {
+ enum Architecture architecture = 1;
+ enum ComputeCapabilities compute_capabilities = 2;
+ uint64 memory_size_mb = 3;
+ uint32 num_cores = 4;
+ // complete with specs of GPU
+}
--
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